The present invention generally relates to integrated circuit testing and, more particularly, is related to automating creation of a Boundary-Scan Description Language (BSDL) file.
With advancements in technology, new integrated circuits (ICs) have been developed to perform different logical functions. ICs are packaged into fine pitch, high-count packages so that a single IC may perform an increasing number of logical functions. ICs are tested prior to use to ensure that electrical characteristics and conductivity are within ranges required to perform specified functions. Unfortunately, high density ICs pose unique manufacturing challenges such as, but not limited to, accessibility of test points and high cost of test equipment.
In 1985, a group of European companies formed the Joint European Test Action Group (JETAG) to address IC testing challenges. JETAG called for incorporating hardware into standard components controlled via software, thereby eliminating the need for sophisticated in-circuit test equipment. By 1988, the standard component concept gained momentum in North America and several companies formed the Joint Test Access Group (JTAG) consortium to formalize the standard component concept. Thereafter, in 1990, the Institute of Electrical and Electronic Engineers (IEEE) refined the standard component concept and created the IEEE/ANSI 1149.1 standard, also known as the IEEE Standard Test Access Port and Boundary-scan Architecture.
The IEEE/ANSI 1149.1 standard was developed to provide standard test facilities and test points in ICs to ensure IC compatibility. Compatibility of ICs that are compliant with the 1149.1 standard allows universal testing techniques to be utilized for the compliant ICs. As more people became aware of, and used, the IEEE/ANSI 1149.1 standard, the need for a standard method for describing IEEE/ANSI 1149.1 standard compatible devices, including ICs, was recognized. The IEEE/ANSI 1149.1 standard working group established a subcommittee to develop a device description language to address the need for a standard method for describing IEEE/ANSI 1149.1 compatible devices.
The subcommittee has since developed and approved an industry standard language called Boundary-scan Description Language (BSDL). BSDL is a subset of the VHSIC Hardware Description Language (VHDL), which describes how the IEEE/ANSI 1149.1 standard is implemented in a device and how that device operates. The IEEE/ANSI 1149.1 standard, which is incorporated by reference here in its entirety, describes an in-circuit testing scheme using xe2x80x9cscan registersxe2x80x9d to capture data from input and output pins of the IC. The term xe2x80x9cregisterxe2x80x9d broadly refers to groups of digital logic storage units that are read or written as a unit. For example, a simple register may be constructed from a group of xe2x80x9cflip-flopsxe2x80x9d whose outputs toggle simultaneously in response to a xe2x80x9cclockxe2x80x9d timing signal. In another type of register, called a xe2x80x9cshift register,xe2x80x9d stored values can also be circulated between the storage elements in the register when a particular control signal is pulsed.
Scan registers act as a group of flip-flops until they are switched into a test mode where they become one long shift register. This configuration allows data to be xe2x80x9cclockedxe2x80x9d serially through all of the scan registers and out of an output pin at the same time that new data is being clocked in from an input pin. A detailed discussion of boundary-scan testing and scan registers is provided in xe2x80x9cThe Boundary-Scan Handbookxe2x80x9d by Kenneth P. Parker (Kluwer Academic Publishers, 2d edition) and xe2x80x9cAgilent 3070 Family Boundary-Scan Fundamentals H7230A Opt 210 (E3795C)xe2x80x9d (Agilent Technologies), both of which are also incorporated by reference here in their entirety. Testing systems that use boundary-scan technology in order to facilitate integrated circuit testing, board testing, and/or system level testing are also commercially-available from a variety of vendors including Agilent Technologies Inc.; Corelis, Inc.; ASSET InterTech, Inc.; JTAG Technologies B.V., Goepel Electronics; Teredyne Inc.; Agere Systems; Sightsys LTD.; Intellitech Corp.; Acugen Software; and others.
Examples of devices that implement the IEEE/ANSI 1149.1 standard in an IC include, but are not limited to, JTAG driving devices and JTAG receiving devices, wherein the devices are registers. The JTAG devices may be utilized for testing electrical characteristics and conductivity of the IC in which the JTAG devices are located.
Unfortunately, creating BSDL files is a tedious and error prone process since IC designers are required to map pin names of ICs to corresponding JTAG driving devices and receiving devices. Mapping of ICs is currently performed by observing netlists utilized for top-level design and by manually determining which top-level port of the IC is associated with which JTAG device.
In light of the foregoing, the preferred embodiment of the present invention generally relates to a system for generating a boundary-scan description language file for an integrated circuit.
Generally, with reference to the structure of the data generation system, the system utilizes a memory; software stored within the memory defining functions to be performed by the system; and a processor. The processor is configured by the software to perform the steps of: creating a flat netlist that describes the integrated circuit, wherein the flat netlist comprises connectivity information regarding leaf cells within the integrated circuit; determining and storing a name provided for each joint test action group register located within the integrated circuit, from the created flat netlist; determining relationships between each joint test action group register located within the integrated circuit and at least one input/output pin located within the integrated circuit, from the created flat netlist, and storing a description of the relationships; and creating a boundary-scan description language file from the stored names of each joint test action group and the stored description of the relationship between the joint test action group register and the input/output pin.
The present invention can also be viewed as providing a method for generating a boundary-scan description language file for an integrated circuit. In this regard, the method can be broadly summarized by the following steps: creating a flat netlist that describes the integrated circuit, wherein the flat netlist comprises connectivity information regarding leaf cells within the integrated circuit; determining and storing a name provided for each joint test action group register located within the integrated circuit, from the created flat netlist; determining relationships between each joint test action group register located within the integrated circuit and at least one input/output pin located within the integrated circuit, from the created flat netlist, and storing a description of the relationships; and creating a boundary-scan description language file from the stored names of each joint test action group and the stored description of the relationship between the joint test action group register and the input/output pin.
Other systems and methods of the present invention will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present invention, and be protected by the accompanying claims.